View STDVE001A_4245953.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STDVE001A
Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer
Preliminary Data
Features

Compatible with the high-definition multimedia interface (HDMI) v1.3 digital interface Conforms to the transition minimized differential signaling (TMDS) voltage standard on input and output channels 340 MHz maximum clock speed operation supports all video formats with deep color at maximum refresh rates 3.4 Gbps data rate per channel Fully automatic adaptive equalizer for cables lengths up to 25 m Single supply VCC: 3.135 to 3.465 V ESD: 8 KV contact for all I/Os Integrated open-drain I2C buffer for display data channel (DDC) 5.3 V tolerant DDC and HPD I/Os Lock-up free operation of I2C bus 0 to 400 kHz clock frequency for I2C bus Low capacitance of all the channels Equalizer regenerates the incoming attenuated TMDS signal Buffer drives the TMDS outputs over long PCB track lengths Low output skew and jitter Tight input thresholds reduce bit error rates On-chip selectable 50 input termination Low ground bounce Data and control inputs provide undershoot clamp diode
TQFP48 QFN48

Description
The STDVE001A integrates a 4-channel 3.4 Gbps TMDS equalizer. High-speed data paths and flowthrough pinout minimize the internal device jitter and simplify the board layout. The equalizer overcomes the intersymbol interference (ISI) jitter effects from lossy cables. The buffer/driver on the output can drive the TMDS output signals over long distances. In addition to this, STDVE001A integrates the 50 termination resistor on all the input channels to improve performance and reduce board space. The device can be placed in a low-power mode by disabling the output current drivers. The STDVE001A is ideal for advanced TV and STB applications supporting HDMI/DVI standard. The differential signal from the HDMI/DVI ports can be routed through the STDVE001A to guarantee good signal quality at the HDMI receiver. Designed for very low skew, jitter and low I/O capacitance, the switch preserves the signal integrity to pass the stringent HDMI compliance requirements.
Evaluation kit is available Table 1. Device summary
Order code STDVE001ABTR STDVE001AQTR Operating temperature -40C to 85C -40C to 85C Package TQFP48 QFN48 Packaging Tape and reel Tape and reel
July 2008
Rev 2
1/49
www.st.com 49
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STDVE001A
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 4.2 4.3 4.4 4.5 4.6 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 26 DC electrical characteristics (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 30
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1 5.2 5.3 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.1 I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 7
2/49
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STDVE001A
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Adaptive equalizer gain with frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OE_N operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC specifications for TMDS differential ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs . . . . . . . 23 Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Status pins (HPD_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Status pins (HPD_EXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC electrical characteristics (CEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Status pins (HPD_INT, HPD_EXT, OE_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TQFP48 (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 QFN48 (7 x 7 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
List of figures
STDVE001A
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. STDVE001A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STDVE001A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin configuration (TQFP48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin configuration (QFN48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STDVE001A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TQFP48 (7 x 7 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TQFP48 (7 x 7 mm) footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TQFP48 (7 x 7 mm) tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 QFN48 (7 x 7 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4/49
STDVE001A
Block diagram
1
Block diagram
Figure 1. STDVE001A block diagram
5/49
Block diagram Figure 2. Equalizer functional diagram (one signal pair)
STDVE001A
EQ_BOOST 1, 2 OE_N PRE Data+ 50 Termination Selectable Pre-Amp Equalizer Quantizer Output I Driver
Data-
OE_N REXT
Output current control
AM00720V2
Figure 3.
DDC I2C bus repeater
6/49
STDVE001A
Block diagram
1.1
Application diagrams
Figure 4. STDVE001A in a digital TV
7/49
Pin configuration
STDVE001A
2
Pin configuration
Figure 5. Pin configuration (TQFP48 package)
8/49
STDVE001A Figure 6. Pin configuration (QFN48 package)
Pin configuration
EQ_BOOST2
EQ_BOOST1
DDC_EN
HPD_INT
VDD_INT 26
SDA_INT
SCL_INT
36
35
34
33
31
30
27
OE_N
GND
GND
VCC
GND
24 23 22 21 20 19 18 17 16 15 14 13
GND OUT_D1OUT_D1+ VCC OUT_D2OUT_D2+ GND OUT_D3OUT_D3+ VCC OUT_D4OUT_D4+
32
29
28
GND IN_D1IN_D1+ VCC IN_D2IN_D2+ GND IN_D3IN_D3+ VCC IN_D4IN_D4+
37 38 39 40 41 42 43 44 45 46 47 48
10 PRE 11 VDD_EXT 2 3 4 1 5 6 7 8 9
QFN-48
CEC_IO
GND
REXT
CEC_IO_INT
HPD_EXT
SDA_EXT
SCL_EXT
VCC
GND
GND
12
25
9/49
Pin configuration
STDVE001A
Table 2.
Pin number 1 2 3 4 5 6
Pin description
Pin name GND VCC CEC_IO CEC_IO_INT GND REXT Type Power Power I/O I/O Power Analog Ground 3.3 V5% DC supply CEC signal to/from the connector end CEC signal to/from TV end Ground Connect to GND through a 4.7 K 1% precision reference resistor. Sets the output current to generate the output voltage compliant with TMDS 0 to 5.0 V (nominal) output signal. Hot plug detector output. Open drain output. Connect an external resistor according to the HDMI specification. DDC data I/O. Pulled-up by external termination to VDD. DDC clock I/O. Pulled-up by external termination to VDD. TMDS output de-emphasis adjustment Function
7 8 9
HPD_EXT SDA_EXT SCL_EXT
Output I/O I/O
PRE 10 PRE Input 0V 3.3 V
Output de-emphasis
0 dB
3 dB
11 12 13 14 15 16 17 18 19 20 21
VDD_EXT GND OUT_D4+ OUT_D4VCC OUT_D3+ OUT_D3GND OUT_D2+ OUT_D2VCC
Power Power Output Output Power Output Output Power Output Output Power
DC supply for DDC, HPD and CEC (can be 5V or 3.3V or unconnected) Ground HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal with OUT_D4-. HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output signal with OUT_D4+. 3.3V10% DC supply HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal with OUT_D3-. HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output signal with OUT_D3+. Ground HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2-. HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output signal with OUT_D2+. 3.3V10% DC supply
10/49
STDVE001A Table 2.
Pin number 22 23 24
Pin configuration Pin description (continued)
Pin name OUT_D1+ OUT_D1GND Type Output Output Power Function HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal with OUT_D1-. HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output signal with OUT_D1+. Ground Active low enable signal
OE_N 25 OE_N Input 1 0
N_D termination
IOUT_D outputs
High-Z 50
High-Z
Active
26 27 28 29
VDD_INT GND SCL_INT SDA_INT
Power Power I/O I/O
DC supply for DDC, HPD and CEC (can be 5V or 3.3V or unconnected) Ground DDC Clock I/O. Pulled-up by external termination to VCC. DDC Data I/O. Pulled-up by external termination to VCC. Sink side, Low-frequency, 0V to 5V (nominal) hot plug detector input signal. Voltage high indicates "plugged" state; voltage low indicates "unplugged" state. High : 5V power signal asserted from source to sink and EDID is ready Low : No 5V power signal is asserted from source to sink or EDID is not ready
30
HPD_INT
Input
31 32
GND DDC_EN
Power Input
Ground I2C repeater enable signal
DDC_EN
I2C repeater
0V
Disabled, high-Z
3.3 V 33 VCC Power 3.3 V10% DC supply
Enabled, active
11/49
Pin configuration Table 2.
Pin number
STDVE001A Pin description (continued)
Pin name Type Function TMDS input equalization selector (control pin).
EQ_BOOST EQ_BOOST 2 1 34-35 EQ_BOOST1, EQ_BOOST2 Input 0 0 1 1 0 1 0 1
Setting at 825 MHz 11 dB 9 dB 4 dB 16 dB
36 37
38 39 40 41 42 43 44 45 46 47 48
GND GND IN_D1IN_D1+ VCC IN_D2IN_D2+ GND IN_D3IN_D3+ VCC IN_D4IN_D4+
Power Power Input Input Power Input Input Power Input Input Power Input Input
Ground Ground HDMI 1.3 compliant TMDS input. IN_D1- makes a differential pair with IN_D1+. HDMI 1.3 compliant TMDS input. IN_D1+ makes a differential pair with IN_D1-. 3.3V10% DC supply HDMI 1.3 compliant TMDS input. IN_D2- makes a differential pair with IN_D2+. HDMI 1.3 compliant TMDS input. IN_D2+ makes a differential pair with IN_D2-. Ground HDMI 1.3 compliant TMDS input. IN_D3- makes a differential pair with IN_D3+. HDMI 1.3 compliant TMDS input. IN_D3+ makes a differential pair with IN_D3-. 3.3V10% DC supply HDMI 1.3 compliant TMDS input. IN_D4- makes a differential pair with IN_D4+. HDMI 1.3 compliant TMDS input. IN_D4+ makes a differential pair with IN_D4-.
12/49
STDVE001A
Functional description
3
Functional description
The STDVE001A routes physical layer signals for high bandwidth digital video and is compatible with low voltage differential signaling standard like TMDS. The device passes the differential inputs from a video source to a common display when it is in the active mode of operation. The device conforms to the TMDS standard on both inputs and outputs. The low on-resistance and low I/O capacitance of the switch in STDVE001A result in a very small propagation delay. Additionally, it supports the DDC, HPD and CEC signaling. The I2C interface of the enabled input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the enabled input port is output to HPD_EXT.
3.1
Adaptive equalizer
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation from long or lossy transmission media. The inputs present high impedance when the device is not active or when VCC is absent or 0 V. In all other cases, the 50 termination resistors on input channels are present. This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the gain stage of the equalizer to compensate the signal degradation and then the signals are driven on to the output ports. The equalizer is fully adaptive and automatic in function providing smaller gain at low frequencies and higher gain at high frequencies. The default setting of EQ = 00 is recommended on EQ pins for optimized operation. Table 3.
Freq (MHz) 225 325 410 825 1650
Adaptive equalizer gain with frequency
Gain in dB (EQ=00) 3 5 6.5 11 16 Gain in dB (EQ=01) 2 3 4.5 9 14 Gain in dB (EQ=10) 0 1 1.5 4 8.5 Gain in dB (EQ=11) 6.5 8.5 11 16 21.5
13/49
Functional description Figure 7. STDVE001A gain vs. frequency
Gain v/s Freq (STDVE001A)
25 20 Gain (dB) 15 10 5 0 225 325 410 Freq (MHz) 825 1650
STDVE001A
Gain (EQ=00) Gain (EQ=01) Gain (EQ=10) Gain (EQ=11)
The equalizer of STDVE001A is fully adaptive and automatic in function. The default setting of EQ = 00 is recommended for optimal operation. The equalizer performance is optimized for all frequencies over the cable lengths from 1m to 25 m at EQ = 00. If cable lengths greater than 25 m are desired in application, then EQ = 11 setting is recommended. The other two EQ settings of 01 and 10 are provided simply for fine-tuning purposes and can be used for very short external cables or PCB traces only if deemed necessary.
Input termination
The STDVE001A integrates precise 50 5% termination resistors, pulled up to VCC, on all its differential input channels. External terminations are not required. This gives better performance and also minimizes the PCB board space. These on-chip termination resistors should match the differential characteristic impedance of the transmission line. Since the output driver consists of current steering devices, an output voltage is not generated without a termination resistor. Output voltage levels are dependent on the value of the total termination resistance. The STDVE001A produces TMDS output levels for point-to-point links that are doubly terminated (100 at each end). With the typical 10 mA output current, the STDVE001A produces an output voltage of 3.3 - 0.5 V = 2.8 V when driving a termination line terminated at each end. The input terminations are selectable thus saving power for the unselected ports.
Output buffers
Each differential output of the STDVE001A drives external 50 load (pull-up resistor) and conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential current-steering devices. The driver outputs are short-circuit current limited and are high-impedance to ground when OE_N = H or the device is not powered. The current steering architecture requires a resistive load to terminate the signal to complete the transmission loop from VCC to GND through the termination resistor. Because the device switches the direction of the current flow and not voltage levels, the output voltage swing is determined by VCC minus the voltage drop across the termination resistor. The output current drivers are controlled by the OE_N pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate internal current mirrors of a stable reference current which is generated by band-gap voltage across the REXT. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 termination resistor.
14/49
STDVE001A
Functional description
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point communication over a tightly controlled impedance medium. The TMDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The device is capable of detecting differential signals as low as 100 mV within the entire common mode voltage range.
3.2
Operating modes
Table 4. OE_N operating modes
Input OE_N L L H IN+ H L X INL H X Output Function OUT+ H L Hi-Z OUTL H Hi-Z Active mode Active mode Low power mode
The OE_N input activates a hardware power down mode. When the power down mode is active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off and disabled. Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a delay associated with turning on band-references and input/output buffer circuits. Note that the OE_N pin is only used to disable the TMDS paths in the chip to same maximum amount of current. It does not affect the HPD, DDC and CEC portions. The DDC is controlled only by the DDC_EN pin whereas the HPD and CEC are always active as long as the supply to the chip is present.
15/49
Functional description
STDVE001A
3.3
HPD pins
The input pin HPD_INT is 5 V tolerant, allowing direct connection tp 5 V signals. The output HPD pin has open-drain structure so that the disabled HPD output is driven to GND whereas the enabled HPD port has the same polarity as the HPD_INT. Note that the HPD output should have an external pull-up resistor connected to +5 V from the HDMI source.
3.4
DDC channels
The DDC channels are designed together with a bi-directional buffer so as to ensure the voltage levels on the I2C lines are met even after long capacitive cables. This feature eliminates the errors during EDID and HDCP reading.
16/49
STDVE001A
Functional description
3.5
I2C DDC line repeater
The device contains two identical bi-directional open-drain, non-inverting buffer circuits that enable I2C DDC bus lines to be extended without degradation in system performance. The STDVE001A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C bus, while retaining all the operating modes and features of the I2C system. This enables two buses of 400 pF bus capacitance to be connected in an I2C application. These buffers are operational from a supply V of 3.0 V to 3.6 V. The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. The STDVE001A enables the system designer to isolate the two halves of a bus, accommodating more I2C devices or longer trace lengths. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other bus is required. The STDVE001A can be used to run the I2C bus at both 5 V and 3.3 V interface levels. The DDC_EN acts as the enable for the DDC buffer. The DDC_EN line should not change state during an I2C operation, because disabling during bus operation hangs the bus and enabling port may through a bus cycle could confuse the I2C ports being enabled. The DDC_EN input should change state only when the global bus and repeater port are in idle state, to prevent system failures. The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lock-up condition from occurring when the input low condition is released. As with the standard I2C system, pull up resistors are required to provide the logic high levels on the buffered bus. The STDVE001A has standard open collector configuration of the I2C bus. The size of the pull up resistors depends on the system, but each side of the repeater must have a pull up resistor. This part is designed to work with standard mode and fast mode I2C devices. Standard mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA in a generic I2C system where standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.
3.6
Power-down condition
The OE_N pin can be used to disable the device. Also there is no ESD protection dode to supply on any of the IOs. This prevents a reverse current flow condition when the main box is switched off while the TV is switched on. The OE_N is used to disable most of the internal circuitry of STDVE001A that puts the device in a low power mode of operation.
17/49
Functional description
STDVE001A
3.7
Bias
The bandgap reference voltage over the external REXT reference resistor sets the internal bias reference current. This current and its factors (achieved by employing highly accurate and well matched current mirror circuit topologies) are generated on-chip and used by several internal modules. The 10 mA current used by the transmitter block is also generated using this reference current. It is important to ensure that the REXT value is within the 1% tolerance range of its typical value. Table 5. Bias parameter
Min Typ 1.2 Max Unit V
Parameter Bandgap voltage
The output voltage swing depends on 3 components: supply voltage (Vsupply), termination resistor (RT) and current drive (Idrive). The supply voltage can vary from 3.3 V 5%, termination resistor can vary from 50 10%.
The voltage on the output is given by: Vsupply -Idrive x RT. The variation on Idrive must be controlled to ensure that the voltage on HDMI output is within the HDMI specification under all conditions. This is achieved when: 400 mV Idrive x RT 600 mV with typical value centered at 500 mV.
3.8
Timing between HPD and DDC
It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is complete. As soon as the discovery is finished by the HPD detection, the configuration data is exchanged between a source and sink through the I2C DDC interface. The STDVE003 Afs DDC interface is ready for communication as soon as the power supply to the chip is present and stable. When the desired port is enabled and the chip is out of shutdown mode, the I2C DDC lines can be used for communication. Thus, as soon as the HPD detection sequence is complete, the DDC interface can be readily used. There is no delay between the HPD detection and I2C DDC interface to be ready.
18/49
STDVE001A
Functional description
3.9
CEC
The CEC channel is a dedicated single pin bus and electrically translates to a bi-directional buffer used to ensure that the electrical specs of the CEC are met even with high capacitance on the single CEC line. The pull-up resistor of 26K? is integrated on either sides of the buffer. The CEC is used for AV control of the electronic devices connected in a HDMI cluster. The drive of the buffer is set to meet the requirements of the CEC. This is optionally used for higher-level user functions such as automatic set-up tasks or tasks typically associated with infrared remote control usage. The CEC line is continuously monitored during the power-on state and is not monitored during powered-off state. In powered off state, the CEC line should not be pulled low and it should not affect the CEC communication between other devices. The maximum capacitance on the CEC lines can be 7.2nF.
19/49
Maximum rating
STDVE001A
4
Maximum rating
Stressing the device above the rating listed in the "absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol
VCC
Absolute maximum ratings
Parameter Supply voltage to ground DC input voltage (TMDS ports) Value -0.5 to +4.0 1.7 to +4.0 -0.5 to +4.0 -0.5 to +6.0 120 -65 to +150 300 8 Unit V V V V mA C C kV
VI
OE_N, DDC_EN, PRE, EX_BOOST1, EX_BOOST2 SDA_INT, SCL_INT, SDA_EXT, SCL_EXT, HPD_INT, HPD_EXT
IO TSTG TL VESD
DC output current Storage temperature Lead temperature (10 sec) Contact discharge Electrostatic discharge voltage on all IOs as per IEC610004-2 standard
Table 7.
Symbol JA
Thermal data
Parameter Thermal coefficient (junction-ambient) TQFP48 QFN48 48 Unit C/W
20/49
STDVE001A
Maximum rating
4.1 4.2
Recommended operating conditions DC electrical characteristics
TA = -40 to +85 C, VCC = 3.3 V 5% (a)
Table 8.
Symbol VCC
Power supply characteristics
Value Parameter Supply voltage All inputs/outputs are enabled. Inputs are terminated with
50 to VCC. VCC = 3.465 V
Test condition Min 3.135 Typ 3.3 Max 3.465
Unit V
ICC
Supply current
130
mA
Data rate = 3.4 Gbps
Table 9.
Symbol
DC specifications for TMDS differential inputs
Value Parameter Differential input high threshold (peak-to-peak) Differential input low threshold Differential input voltage (peak-to-peak)(1) Common mode voltage range Input capacitance IN+ or IN- to GND F = 1 MHz Test condition Min VCC = 3.465 V over the entire VCMR VCC = 3.465 V over the entire VCMR VCC = 3.465 V -150 Typ Max Unit
VTH
0
150
mV
VTL
0
mV
VID
150
1560
mV
VCMR
VCC - 0.3
VCC - 0.04
V
CIN
3.5
pF
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |.
a. Typical parameters are measured at VCC = 3.3 V, TA = +25 C.
21/49
Maximum rating Table 10.
Symbol
STDVE001A
DC specifications for TMDS differential ouputs
Value Parameter Single-ended high level output voltage Single-ended low level output voltage Single ended output swing voltage Differential output voltage (peak-to-peak)(1) Differential output high level current Differential output low level current Output driver shortcircuit current (continuous) OUT = GND through a 50 resistor. See Figure 12 OUT+ or OUTto GND when tristate F = 1 MHz VCC = 3.3 V RTERM = 50 VCC = 3.3 V RTERM = 50 Test condition Min Typ Max VCC+10 VCC-400 500 600 mV mV mV Unit
VOH VOL Vswing
VCC-10 VCC-600 400
VOD
800
1000
1200
mV
IOH IOL
0 8 10
50 12
A mA
|ISC|
12
mA
COUT
Output capacitance
5.5
pF
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |
22/49
STDVE001A Table 11.
Symbol
Maximum rating
DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs
Value Parameter Test condition Min Typ Max V 0.8 -0.8 +5 +5 3.5 V V A A pF High level guaranteed Low level guaranteed VCC = 3.465 V IIN = -18 mA VCC = 3.465 V VIN = VCC VCC = 3.465 V VIN = GND Pin to GND F = 1 MHz Unit
VIH VIL VIK IIH IIL CIN
HIGH level input voltage LOW level input voltage Clamp diode voltage Input high current Input low current Input capacitance
2.0 -0.5 -1.2 -5 -5
Table 12.
Symbol
Input termination resistor
Parameter Differential input termination resistor on IN channels relative to VCC Test condition Value Unit
RTERM
IIN = -10 mA
45
50
55
Table 13.
Symbol
External reference resistor
Value Parameter Resistor for TMDS compliant voltage swing range Test condition Min Typ 4.7 Max K Unit
REXT
Tolerance for R = 1%
Table 14.
Symbol VI(DDC)
DDC I/O pins
Value Parameter Input voltage Test condition Min GND Typ Max 5.3 V Unit
23/49
Maximum rating Table 14.
Symbol
STDVE001A
DDC I/O pins
Value Parameter Test condition Min VCC = 3.465 V Input port= 5.3 V Output port = 0.0 V Switch is isolated Typ Max Unit
6
A
II(leak)
Input leakage current VCC = 3.465 V Input port = 3.3 V Output port = 0.0 V Switch is isolated VI = 0 V F = 1 MHz Switch disabled 5 2 A
pF
CI/O
Input/output capacitance VI = 0 V F = 1 MHz Switch enabled 9 pF
24/49
STDVE001A
Maximum rating
Table 15.
Symbol
Status pins (HPD_INT)
Value Parameter Test condition Min Typ Max 5.3 0.8 4 2 V V A A VCC = 3.3 V High level guaranteed VCC = 3.3 V Low level guaranteed VCC = 3.465 V Output = 5.3 V Unit
VIH VIL
High level input voltage Low level input voltage
2.0 GND
II(leak)
Input leakage current VCC = 3.465 V Output = 3.3 V
Table 16.
Symbol V
Status pins (HPD_EXT)(1)
Value Parameter Voltage VI = 0 V F = 1 MHz Switch disabled Test condition Min GND 5 Typ Max 5.3 V pF Unit
CI/O
Input/output capacitance VI = 0 V F = 1 MHz Switch enabled Output low voltage (open drain I/Os) VCC = 3.3 V IOL = 8 mA 9 pF
VOL
0.4
V
1. Typical parameters are measured at VCC = 3.3 V, TA = +25 C.
25/49
Maximum rating
STDVE001A
4.3
Table 17.
Symbol
DC electrical characteristics (I2C repeater)
(TA = -40 to +85 C, VCC = 3.3 V 5%, GND = 0 V; unless otherwise specified) Supplies
Value Parameter Test condition Min VCC DC supply voltage 3.135 Typ 3.3 Max 3.465 V Unit
Table 18.
Symbol
Input/output SDA, SCL
Value Parameter High level input voltage Low level input voltage(1) Low level input voltage contention(1) Input clamp voltage Input current low (SDA, SCL) II = -18 mA Input current low (SDA, SCL) VI = 3.465 V (SDA, SCL) VI = 5.3 V (SDA, SCL) IOL = 3 mA IOL = 6 mA VO = 3.6 V; driver disabled VO = 5.3 V; driver disabled VI = 3 V or 0 V Test condition Min Typ Max 5.3 0.3 VCC 0.4 V V V V A A A V V A A pF Unit
VIH VIL VILc VIK IIL
0.7 VCC -0.5 -0.5
- - - -
- - - -
-1.2 1 10 10 0.4 0.65
IIH
Input current high (SDA, SCL)
VOL
LOW-level output voltage
IOH
Output high level leakage current
- - -
- -
6
10 10 7(2)
CI
Input capacitance
1. VIL specification is for the first low level seen by the SDA/SCL lines. VILc is for the second and subsequent low levels seen by the SDA/SCL lines. 2. The SCL/SDA CI is about 200 pF when VCC = 0 V. The STDVE001A should be used in applications where power is secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
26/49
STDVE001A
Maximum rating
4.4
DC electrical characteristics (CEC)
(TA = -40 to +85 C, VCC = 3.3V 5%, GND=0V; unless otherwise specified) Table 19.
Symbol VCC VOL VOH VHL(th) VLH(th) Vhys Tr Tf RPU IOFF
DC electrical characteristics (CEC)
Value Parameter Test condition Min Typ 3.3 Max 3.465 0.6 3.63 Vcec(`0') 0.8 Vcec(`1') 2.0 0.4 CL= 7.2 nF CL= 7.2 nF 23.4 VCC = 0.0 V 26 250 50 28.6 1.8 Unit V V V V V V s s K A 3.135 0.0 2.5
DC supply voltage Logic 0 output Logic 1 output High to low input V treshold for logic `0' Low to high input V treshold for logic `1' Typical input hysteresis(1) Maximum rise time (10% to 90%) Maximum fall time (90% to 10%) Internal pull-up resistor(2) CEC IO current in upowered state
1. Input hysteresis is normally supplied by the microprocessor input circuit. In this case, additional hysteresis circuitry is not needed. 2. The internal device pull-up should be disconnected from the line when the device is powered-off.
27/49
Maximum rating
STDVE001A
4.5
Dynamic switching characteristics(b)
TA = -40 to +85 C, VCC = 3.3 V 5%, RTERM = 50 5%, CL = 5 pF). Typical values are at TA = +25 C and VCC = 3.3 V.
Table 20.
Symbol
Clock and data rate
Value Parameter Clock frequency (1/10th of the differenttial data rate) Signaling rate Test condition Min Typ Max 340 3.4 MHz Gbps Unit
fCK Drate
25
Table 21.
Symbol tr tf tPLH tPHL
Differential output timings
Value Parameter Differential data and clock output rise/fall times Differential low to high propagation delay Differential high to low propagation delay Test condition Min 20% to 80% of VOD 80% to 20% of VOD Alternating 1 and 0 pattern at slow and fast data rates Measure at 50% VOD between input to output 75 75 250 250 Typ 150 150 Max 240 240 800 800 ps ps ps ps Unit
Table 22.
Symbol
Skew times
Value Parameter Inter-pair channel-tochannel output skew Pulse skew Intra-pair differential skew Difference in propagation delay (tPLH or tPHL) among all output channels | tPLH - tPHL | 25 Test condition Min Typ Max 100 80 44 ps ps ps Unit
tSK(O) tSK(P) tSK(D)
tSK(CC)
Output channel to channel skew
50
125
ps
b.
The timing values in this section are tested during characterization and are guaranteed by design and simulation. Not tested in production.
28/49
STDVE001A Table 23.
Symbol
Maximum rating
Turn-on and turn-off times
Value Parameter Test condition Min TMDS output enable time Time from OE_N to OUT change from tristate to active Time from OE_N to OUT change from active to tristate Typ Max Unit
tON
12
20
ns
tOFF
TMDS output disable time
6
10
ns
Table 24.
Symbol
DDC I/O pins
Value Parameter Test condition Min Refer to Section 4.6 Typ Max Unit
Table 25.
Symbol
Status pins (HPD_INT, HPD_EXT, OE_N)
Value Parameter Propagation delay (from Y_HPD to the active port of HPD) Test condition Min Typ 150 Max ns Unit
tPD(HPD)
CL = 10 pF, RPU = 1 K
TON/OFF
Switch time (from port select to the CL = 10 pF latest valid status of HPD)
50
ns
Table 26.
Symbol
Jitter
Value Parameter Test condition Min Typ 35 Max ps (p-p) PRBS pattern at 1.6 Gbps (800 MHz) Unit
tJIT
Total jitter(1)
1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. Input differential voltage = VID = 500 mV, PRBS random pattern at 1.65 Gbps, tr=tf=50 ps (20% to 80%). Jitter parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
29/49
Maximum rating
STDVE001A
4.6
Dynamic switching characteristics (I2C repeater)
TA = -40 to +85 C, VCC = 3.3 V 5%. Typical values are at TA = +25 C and VCC = 3.3 V. . I2C repeater(1)
Value Parameter Test condition Min Typ Max 100 400 kHz kHz Standard mode Fast mode 100 KHz See Figure 20 Voltage on line = 5V Cmax=400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions. Unit
Table 27.
Symbol
fSCL
I2C clock frequency
4.7
s
tLOW
Low duration on SCL pin
400 KHz See Figure 20 Voltage on line = 5V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions. 100 KHz See Figure 20 Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions.
1.3
s
4.7
s
tLOW
Low duration on SCL pin 400 KHz See Figure 20 Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions.
1.3
s
30/49
STDVE001A Table 27.
Symbol
Maximum rating
I2C repeater(1) (continued)
Value Parameter Test condition Min 100 KHz See Figure 20 Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions Typ Max Unit
4.0
s
tHIGH
High duration on SCL pin 400 KHz See Figure 20 Voltage on line = 5 V Cmax = 400 pF, Rmax=2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions 100 KHz Refer section 14.12, Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions
0.6
s
4.0
s
tHIGH
High duration on SCL pin 400 KHz See Figure 20 Voltage on line = 3.3 V, Cmax=400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions 400 KHz Waveform 1 (Figure 18) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 400 KHz Waveform 1 (Figure 18) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 400 KHz Waveform 1 (Figure 18) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K
0.6
s
tPHL
Propagation delay
250
s
tPLH
Propagation delay
300
s
tPHL
Propagation delay
250
ns
31/49
Maximum rating Table 27.
Symbol
STDVE001A
I2C repeater(1) (continued)
Value Parameter Test condition Min 400 KHz Waveform 1 (Figure 18) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 18) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 18) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 18) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 18) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 400 KHz Waveform 1 (Figure 18)(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Typ Max Unit
tPLH
Propagation delay
450
ns
tPHL
Propagation delay
250
ns
tPLH
Propagation delay
300
ns
tPHL
Propagation delay
250
ns
tPLH
Propagation delay
450
ns
300
ns
tf
Output fall time 400 KHz Waveform 1(2) Voltage on li ne = 3.3 V Cmax = 400pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 18) (2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 300 ns
300
ns
tf
Output fall time 100 KHz Waveform 1 (Figure 18)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 300 ns
32/49
STDVE001A Table 27.
Symbol
Maximum rating
I2C repeater(1) (continued)
Value Parameter Test condition Min 400 KHz Waveform 1 (Figure 18)(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Typ Max Unit
300
ns
tr
Output rise time 400 KHz Waveform 1 (Figure 18)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1,(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 300 ns
1000
ns
tr
Output rise time 100 KHz Waveform 1 (Figure 18)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 1000 ns
1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in production. 2. The tr transition time is specified with maximum load of 2 k pull-up resistance and 400 pF load capacitance. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. Refer to Figure 10.
Table 28.
Symbol ESD
ESD performance
Parameter All I/Os Test conditions Contact discharge as per IEC61000-4-2 standard Min Typ 8 Max Unit kV
33/49
Maximum rating Figure 8. Test circuit for electrical characteristics
STDVE001A
VCC CL VOUT+
VIN+
Pulse generator
RT RT
VIN-
STDVE001A
VOUTCL
100
AM00726V1
1. CL = load capacitance: include jig and probe capacitance. 2. RT = termination resistance; should be equal to ZOUT of the pulse generator.
Figure 9.
TMDS output driver
VCC
RT ZO = RT
RT
TMDS driver
ZO = RT
TMDS receiver
CS00069
1. ZO = characteristic impedance of the cable. 2. RT = termination resistance: should be equal to ZO of the cable. Both are equal to 50W.
34/49
STDVE001A Figure 10. Test circuit for HDMI receiver and driver
Maximum rating
VCC
RT A VID B
RT Y TMDS receiver TMDS driver CL = 0.5pF VY Z
RT
VA
VCC
VB
VID = VA - VB
VSwing = VY - VZ
VZ
RT
CS00071
1. RT = 50 .
35/49
Maximum rating Figure 11. Test circuit for turn off and turn off times
STDVE001A
10F
0.1 F 0.01F
1.15 V VIN+ 1.0 V
CL VCC
50 1.2 V
1.15 V VIN1.0 V
STDVE001A
50
SHDN_N CL GND 4.7 K1%
REXT Pulse generator 50
AM00727V1
1. CL = 5 pF
Figure 12. Test circuit for short circuit output current
50 ISC TMDS driver 50
0V or 3.465 V
36/49
STDVE001A Figure 13. Propagation delays
VA VCC
Maximum rating
VCM
VID
VCM VCC - 0.4
VB
0.4V VID 0V
VID
VID(p-p)
-0.4V
tpLH 80%
VOD(O)
tpHL 100% 80% 0V Differential
VOD(p-p)
20% Output
20% 0% VOD(U)
tr
tf
Figure 14. Turn-on and turn-off times
SHDN_N 1.50 V 1.50 V 0V tOFF tON VOH VOUT+ when VID= +150mV VOUT- when VID= -150mV 50% 50% 1.2 V tOFF tON 1.2 V VOUT+ when VID= -150mV VOUT- when VID= +150mV 50% 50% VOL 3.0 V
37/49
Maximum rating Figure 15. TSK(O)
STDVE001A
3.5V
2.5V
Data In
1.5V tpLHX tpHLX
VOH
2.5V 2.5V
Data Out at Port 0 VOL tSK(o) VOH
2.5V
Data Out at Port 1 VOL tpLHY tpHLY
tSK(o) = | tpLHy - tpLHx | or | tpHLy - tpHLx |
Figure 16. TSK(P)
Figure 17. TSK(D)
38/49
STDVE001A Figure 18. AC waveform 1 (I2C lines)
Maximum rating
Figure 19. Test circuit for AC measurements (I2C lines)
Figure 20. I2C bus timing
39/49
Application information
STDVE001A
5
5.1
Application information
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to always apply VCC before applying any signals to the input/output or control pins.
5.2
Power supply requirements
Bypass each of the VCC pins with 0.1 F and 1 nF capacitors in parallel as close to the device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as possible. All VCC pins can be tied to a single 3.3 V power source. A 0.01 F capacitor is connected from each VCC pin directly to ground to filter supply noise. The maximum power supply variation can only be 5% as per the HDMI specifications. The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
5.3
Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several considera-tions to minimize discontinuities on these transmission lines between the connectors and the device. (a) Maintain 100- differential transmission line impedance into and out of the STDVE001A. (b) Keep an uninterrupted ground plane below the high-speed I/Os. (c) Keep the ground-path vias to the device as close as possible to allow the shortest return current path. (d) Layout of the TMDS differential inputs should be with the shortest stubs from the connectors. Output trace characteristics affect the performance of the STDVE001A. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. Run the differential traces close together to minimize the effects of the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to further prevent impedance discontinuities.
40/49
STDVE001A
Application information
5.3.1
I2C lines application information
A typical application is shown in the figure below. In the example, the system master is running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz. Master devices can be placed on either bus. Figure 21. Typical application of I2C bus system
3.3V 5.0V
SDA SCL Bus master 400 kHz
SDA SCL
SDA SCL
SDA SCL Slave 100 kHz
STDVE 001 A
BUS 0
BUS 1
The STDVE001A DDC lines are 5 V tolerant; so it does not require any extra circuitry to translate between the different bus voltages.
41/49
Package mechanical data
STDVE001A
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 22. TQFP48 (7 x 7 mm) package outline
42/49
STDVE001A Table 29. TQFP48 (7 x 7 mm) mechanical data
Millimeters Symbol Min A A1 A2 D D1 E E1 L L1 T T1 a b b1 e ccc / ddd 0.70 0.10 0 0.17 0.17 0.22 0.20 0.500 0.08 0.05 0.95 8.80 6.90 8.80 6.90 0.45 0.10 1.00 9.00 7.00 9.00 7.00 0.60 1.00 0.15 0.13 Typ
Package mechanical data
Max
0.15 1.05 9.20 7.10 9.20 7.10 0.75
0.20 1.15 7 0.27 0.23
43/49
Package mechanical data Figure 23. TQFP48 (7 x 7 mm) footprint recommendation
STDVE001A
44/49
STDVE001A Figure 24. TQFP48 (7 x 7 mm) tape and reel information
Package mechanical data
45/49
Package mechanical data Figure 25. QFN48 (7 x 7 mm) package outline
STDVE001A
46/49
STDVE001A
Package mechanical data
Table 30.
QFN48 (7 x 7 mm) package mechanical data
Millimeters
Symbol Min A A1 A2 A3 b D D2 E E2 e L ddd 0.18 6.85 2.25 6.85 2.25 0.45 0.30 0.80 Typ 0.90 0.02 0.65 0.25 0.23 7.00 4.70 7.00 4.70 0.50 0.40 0.30 7.15 5.25 7.15 5.25 0.55 0.50 0.08 Max 1.00 0.05 1.00
47/49
Revision history
STDVE001A
7
Revision history
Table 31.
Date 02-Jul-2008 21-Jul-2008
Document revision history
Revision 1 2 Initial release. Modified: Figure 2 and Section 3: Functional description on page 13 Replaced `equation' with `equalizer in the Features section. Changes
48/49
STDVE001A
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
49/49

▲Up To Search▲

Price & Availability of STDVE001A

	To Download STDVE001A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .